Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain.
A Flash device that utilizes the ONO structure is a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell. The MONOS type cell includes a bit-line, a word line and an ONO structure which function together to determine the location of the bit stored in memory. Important factors towards achieving high performance of the MONOS type cell include the quality and cleanliness of the ONO structure.
A problem exists with known MONOS fabrication techniques in that a quality and cleanliness of the ONO structure cannot be guaranteed during the fabrication process of the transistor. One reason that these factors cannot be guaranteed is that during production of the MONOS type cell, the top oxide layer of the ONO structure is subjected to repeated photoresist coatings and cleanings. For example, a resist layer is formed on the ONO structure to protect the device during boron and arsenic implants that underlie the bit-line. After the boron and arsenic are implanted, typically ashing and a wet clean are used to remove the resist layer. Thereafter, to form other parts of the transistor, for example, at the periphery, additional photoresist coatings and cleanings are performed on the ONO structure.
To effectively remove the resist layer, the top oxide layer should be aggressively cleaned so that an organic residue of the resist material does not contaminate the top oxide of the ONO structure. Resist material remaining on the top oxide layer of the ONO structure can adversely effect the connection between the top oxide layer and an overlying polycrystalline silicon layer of the MONOS cell to degrade performance of the cell. According to known MONOS type cell structures, however, cleaning cannot be accomplished with an aggressive acid, such as hydrofluoric acid, since the aggressive acid can degrade the top oxide layer of the ONO structure.
In sum, while there have been recent advances in EEPROM technology, numerous challenges exist in the fabrication of these devices. In particular, there is a need for an improved method of generating a MONOS type Flash cell and EEPROM technology that allows for aggressive cleaning of a top layer of the ONO structure. In addition, the improved method should ensure a high quality ONO structure, e.g., one that can withstand multiple photresist coatings and cleanings without degrading a top layer of the ONO structure.